Achievement of low temperature chip stacking by a wafer-applied underfill material

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 1858-1863

  Cheng, Ren Shin ^a   Kao, Kuo Shu ^a   Chang, Jing Yao ^a   Hung, Yin Po ^a   Yang, Tsung Fu ^a   Huang, Yu Wei ^a   Chen, Su Mei ^a   Chang, Tao Chih ^a   Huang, Qiaohong ^b   Guino, Rose ^b   Hoang, Gina ^b   Bai, Jie ^b   Becker, Kevin ^b  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b HENKEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSEMBLY TECHNOLOGY; BONDING TEMPERATURES; CHIP STACKING; CONTACT AREAS; DIRECT BONDING; FAILURE MECHANISM; INTERFACIAL FRACTURE; LIFE SPAN; LOW TEMPERATURES; PB FREE SOLDERS; PB-FREE SOLDER ALLOYS; RESIDUAL THERMAL STRESS; SOLDER ALLOYS; TEMPERATURE CYCLING TESTS; TEST VEHICLE; UNDERFILL MATERIALS; UNDERFILLS; WAFER APPLIED UNDERFILL; WAFER DICING;

BONDING; FAILURE ANALYSIS; FRACTURE; SILICON WAFERS; SILVER; SILVER ALLOYS; SOLDERING ALLOYS; TECHNOLOGY;

WAFER BONDING;

EID: 79960432904     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898768     Document Type: Conference Paper

References (8)

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