Satisfiability modulo graph theory for task mapping and scheduling on multiprocessor systems

IEEE Transactions on Parallel and Distributed Systems

Volumn 22, Issue 8, 2011, Pages 1382-1389

  Liu, Weichen ^a   Gu, Zonghua ^b   Xu, Jiang ^a   Wu, Xiaowen ^a   Ye, Yaoyao ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^b ZHEJIANG UNIVERSITY   (China)

Author keywords

design space exploration; Multiprocessor; satisfiability; scheduling

Indexed keywords

BRANCH AND BOUNDS; CYCLE ACCURATE; DESIGN SPACE EXPLORATION; DESIGN SPACES; MULTI PROCESSOR SYSTEMS; MULTIPROCESSOR; MULTIPROCESSOR SCHEDULING PROBLEMS; NETWORK ON CHIP; NP-HARD; OPTIMAL SOLUTIONS; OPTIMIZATION FRAMEWORK; PERFORMANCE EVALUATION; PERFORMANCE IMPROVEMENTS; SAT SOLVERS; SATISFIABILITY; SCHEDULING ANALYSIS; SOLUTION SPACE; SYSTEMC; TASK GRAPH SCHEDULING; TASK MAPPING;

EMBEDDED SYSTEMS; FORMAL LOGIC; GRAPH THEORY; LINEAR PROGRAMMING; MAPPING; MULTIPROCESSING SYSTEMS; OPTIMIZATION; PROBLEM SOLVING; SPACE RESEARCH; VLSI CIRCUITS;

SCHEDULING;

EID: 79959726381     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2010.204     Document Type: Article

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