Double-data-rate, wave-pipelined interconnect for asynchronous NoCs

IEEE Micro

Volumn 29, Issue 3, 2009, Pages 20-30

  Xu, Jiang ^a   Wolf, Wayne ^b   Zhang, Wei ^c  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^c PRINCETON UNIVERSITY   (United States)

Author keywords

Asynchronous; Clocks; Delay; Double data rate; Integrated circuit interconnections; Interconnect; Low power; Multiprocessor; Network on chip; Pipeline processing; Receivers; Synchronization; System on chip; Wave pipeline; Wires

Indexed keywords

ASYNCHRONOUS; DELAY; DOUBLE DATA RATE; INTEGRATED CIRCUIT INTERCONNECTIONS; INTERCONNECT; LOW POWER; MULTIPROCESSOR; NETWORK ON CHIP; PIPELINE PROCESSING; RECEIVERS; SYSTEM ON CHIP; WAVE PIPELINE;

CLOCKS; DATA COMPRESSION; DISTRIBUTED COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS; PIPELINES; PROGRAM COMPILERS; WIRE;

INTEGRATED CIRCUITS;

EID: 67650485898     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/MM.2009.40     Document Type: Article

References (8)

1. B. Towles and W.J. Dally, "Route Packets, Not Wires: On-Chip Interconnect Networks," Proc. 38th Design Automation Conf. (DAC 01), IEEE CS Press, 2001, pp. 684-689.
2. J. Cong, "An Interconnect-centric Design Flow for Nanometer Technologies," Proc. IEEE, vol. 89, no. 4, Apr. 2001, pp. 505-528.
3. M. Kuhlmann and S.S. Sapatnekar, "Exact and Efficient Crosstalk Estimation," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 7, Jul. 2001, pp. 858-866.
4. T. Meincke et al., "Globally Asynchronous Locally Synchronous Architecture for Large High-Performance ASICs," Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS 99), vol. 2, IEEE Press, 1999, pp. 512-515.
5. T. Chelcea and S.M. Nowick, "Robust Interfaces for Mixed-Timing Systems," IEEE Trans. Very Large Scale Integration Systems, vol. 12, no. 8, Aug. 2004, pp. 857-873.
6. W.P. Burleson et al., "Wave-Pipelining: A Tutorial and Research Survey," IEEE Trans. VLSI Systems, vol. 6, no. 3, Sept. 1998, pp. 464-474.
7. A.B. Kahng et al., "Interconnect Tuning Strategies for High-Performance ICs," Proc. Design, Automation, and Test in Europe (DATE 98), IEEE CS Press, 1998, pp. 471-478.
8. J. Xu et al., "A Design Methodology for Application-Specific Networks-on-Chip," ACM Trans. Embedded Computing Systems, vol. 5, no. 2, May 2006, pp. 263-280.