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Volumn 15, Issue 6, 2011, Pages 665-667

EIRA LDPC codes on FPGA

Author keywords

eIRA codes; error correction codes; error rate floor; FPGA; LDPC codes

Indexed keywords

ALTERNATIVE APPROACH; DOUBLE PRECISION; EIRA CODES; ERROR CORRECTION CODES; ERROR RATE; ERROR-RATE FLOOR; LDPC CODES; LOW-DENSITY PARITY-CHECK CODES; MATRIX;

EID: 79959572651     PISSN: 10897798     EISSN: None     Source Type: Journal    
DOI: 10.1109/LCOMM.2011.040711.110336     Document Type: Article
Times cited : (7)

References (9)
  • 1
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    • M. Yang, W. E. Ryan, and Y. Li, "Design of efficiently encodable moderate-length high-rate irregular LDPC codes," IEEE Trans. Commun., vol. 52, no. 4, pp. 564-571, Apr. 2004.
    • (2004) IEEE Trans. Commun. , vol.52 , Issue.4 , pp. 564-571
    • Yang, M.1    Ryan, W.E.2    Li, Y.3
  • 2
    • 0141973664 scopus 로고    scopus 로고
    • Lowering the error-rate floors of moderatelength high-rate irregular LDPC codes
    • July
    • M. Yang and W. E. Ryan, "Lowering the error-rate floors of moderatelength high-rate irregular LDPC codes," in Proc. 2003 Int. Symp. Information Theory, p. 237, July 2003.
    • (2003) Proc. 2003 Int. Symp. Information Theory , pp. 237
    • Yang, M.1    Ryan, W.E.2
  • 3
    • 58049199408 scopus 로고    scopus 로고
    • Design of versatile eIRA codes for parallel decoders
    • Dec.
    • L. Dinoi, F. Sottile, and S. Benedetto, "Design of versatile eIRA codes for parallel decoders," IEEE Trans. Commun., vol. 56, no. 12, pp. 2060-2070, Dec. 2008.
    • (2008) IEEE Trans. Commun. , vol.56 , Issue.12 , pp. 2060-2070
    • Dinoi, L.1    Sottile, F.2    Benedetto, S.3
  • 4
    • 67650670676 scopus 로고    scopus 로고
    • Toward low LDPC-code floors: A case study
    • June
    • Y. Zhang and W. E. Ryan, "Toward low LDPC-code floors: a case study," IEEE Trans. Commun., vol. 57, no. 6, pp. 1566-1573, June 2009.
    • (2009) IEEE Trans. Commun. , vol.57 , Issue.6 , pp. 1566-1573
    • Zhang, Y.1    Ryan, W.E.2
  • 6
    • 23844506274 scopus 로고    scopus 로고
    • Weaknesses of Margulis and Ramanujan-Margulis low-density parity-check codes
    • D. MacKay and M. S. Postol, "Weaknesses of Margulis and Ramanujan-Margulis low-density parity-check codes," Electronic Notes Theoretical Computer Science, vol. 74, 2003.
    • (2003) Electronic Notes Theoretical Computer Science , vol.74
    • MacKay, D.1    Postol, M.S.2
  • 9
    • 33644640388 scopus 로고    scopus 로고
    • A 640-Mb/s 2043-bit programmable LDPC decoder chip
    • Mar.
    • M. Mansour and N. Shanbhag, "A 640-Mb/s 2043-bit programmable LDPC decoder chip," IEEE J. Solid-State Circuits, vol. 41, no. 3, pp. 684-698, Mar. 2006.
    • (2006) IEEE J. Solid-state Circuits , vol.41 , Issue.3 , pp. 684-698
    • Mansour, M.1    Shanbhag, N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.