Lowering the error-rate floors of moderate-length high-rate irregular LDPC codes

IEEE International Symposium on Information Theory - Proceedings

Volumn , Issue , 2003, Pages 237-

  Yang, Michael ^a   Ryan, William E ^a  

^a University of Arizona   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; MATRIX ALGEBRA; PROBABILITY; SIGNAL ENCODING; TURBO CODES;

ERROR-RATE FLOORS; IRREGULAR LOW-DENSITY PARITY-CHECK CODES; SYSTEMATIC SERIAL TURBO CODES;

ERROR DETECTION;

EID: 0141973664     PISSN: 21578096     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/isit.2003.1228251     Document Type: Conference Paper

References (3)

1. T. Richardson, A. Shokrollahi, and R. Urbanke, "Design of capacity-approaching irregular low-density parity-check codes," IEEE Trans. Information Theory, pp. 619-637, Feb. 2001.
2. H. Jin, A. Khandekar, and R. McEliece, "Irregular repeat-accumulate codes," 2nd International Symposium on Turbo Codes & Related Topics, pp. 1-8, Brest, France, Sep. 2000.
3. R. Narayanaswami, "Coded Modulation with Low-Density Parity-Check Codes," M.S. thesis, Texas A&AM University, 2001, Chapter 7.