Toward low LDPC-code floors: A case study

IEEE Transactions on Communications

Volumn 57, Issue 6, 2009, Pages 1566-1573

  Zhang, Yifei ^a   Ryan, William E ^a  

^a University of Arizona   (United States)

Author keywords

Bit pinning; Error floor; IRA code; LDPC code; Trapping set

Indexed keywords

ALGEBRAIC CODES; BCH CODE; CODING TECHNIQUES; COUNTER MEASURES; DECODING COMPLEXITY; ERROR FLOOR; IRA CODE; LDPC CODE; LDPC CODES; LDPC DECODER; LOW SIGNAL-TO-NOISE RATIO; LOW-FLOOR; NEAR-CAPACITY PERFORMANCE; TRAPPING SET;

ACOUSTIC INTENSITY; CODING ERRORS; DECODING; SIGNAL TO NOISE RATIO;

FLOORS;

EID: 67650670676     PISSN: 00906778     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCOMM.2009.06.0700712     Document Type: Article

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