Compact wideband equivalent-circuit model for electrical modeling of through-silicon via

IEEE Transactions on Microwave Theory and Techniques

Volumn 59, Issue 6, 2011, Pages 1454-1459

  Liu, En Xiao ^a   Li, Er Ping ^a   Ewe, Wei Bin ^a   Lee, Hui Min ^a   Lim, Teck Guan ^b   Gao, Shan ^b  

^a INSTITUTE OF HIGH PERFORMANCE COMPUTING   (Singapore)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

3 D integrated circuits (ICs) and packaging; Compact wideband equivalent circuit model; FourierBessel expansion; through silicon via (TSV)

Indexed keywords

3-D INTEGRATED CIRCUITS (ICS) AND PACKAGING; ANALYTICAL FORMULAS; CLOSED FORM; ELECTRICAL MODELING; EQUIVALENT-CIRCUIT MODEL; FOURIERBESSEL EXPANSION; PARASITIC EFFECT; PROXIMITY EFFECTS; RESISTANCE AND INDUCTANCE; STATIC SOLUTIONS; THROUGH SILICON VIAS; THROUGH-SILICON VIA (TSV); WIDE-BAND;

CIRCUIT THEORY; ELECTRONICS PACKAGING; EQUIVALENT CIRCUITS; INTEGRATED CIRCUITS; SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS;

THREE DIMENSIONAL;

EID: 79959254998     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2011.2116039     Document Type: Article

References (15)

1. "International Technology Roadmap for Semiconductors (ITRS)," ITRS, 2009. [Online]. Available: http://public.itrs.net/
2. E.-P. Li, X. Wei, A. C. Cangellaris, E.-X. Liu, and Y. Zhang et al., "Progress review of electromagnetic compatibility analysis technologies for packages, printed circuit boards, and novel interconnects," IEEE Trans. Electromagn. Compat., vol. 52, no. 2, pp. 248-265, May 2010.
3. J. P. Quine, H. F.Webster,H.H. Glascock, II, and R. O. Carlson, "Characterization of via connections in silicon circuit boards," IEEE Trans. Microw. Theory Tech., vol. 36, no. 1, pp. 21-27, Jan. 1988.
4. J. U. Knickerbocker, P. S. Andry, L. P. Buchwalter, A. Deutsch, and R. R. Horton et al., "Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection," IBM J. Res. Develop., vol. 49, no. 4.5, pp. 725-753, 2005. (Pubitemid 41398417)
5. G. V. d. Plas, P. Limaye, A. Mercha, H. Oprins, and C. Torregiani et al., "Design issues and considerations for low-cost 3-D TSV IC technology," in Proc. Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 2010, pp. 148-150.
6. C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, and J. Kim, "High frequency electrical model of through wafer via for 3-D stacked chip packaging," in 1st Electron. Syst. Integration Technol. Conf., Dresden, Germany, Sep. 2006, pp. 215-220. (Pubitemid 351576621)
7. C. Xu, H. Li, R. Suaya, and K. Banerjee, "Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs," IEEE Trans. Electron Devices, vol. 57, no. 12, pp. 3405-3417, Dec. 2010.
8. E.-X. Liu, E.-P. Li, Z. Z. Oo, X. Wei, Y. Zhang, and R. Vahldieck, "Novel methods for modeling of multiple vias in multilayered parallelplate structures," IEEE Trans. Microw. Theory Tech., vol. 57, no. 7, pp. 1724-1733, Jul. 2009.
9. H. A. Wheeler, "Formulas for the skin effect," Proc. IRE, vol. 20, no. 9, pp. 412-424, Sep. 1942.
10. S. Ramo, J. R. Whinnery, and T. VanDuzer, Fields and Waves in Communication Electronics. New York: Wiley, 1965.
11. A. Deutsch, H. H. Smith, C. W. Surovic, G. V. Kopcsay, and D. A. Webber et al., "Frequency-dependent crosstalk simulation for on-chip interconnections," IEEE Trans. Adv. Packag., vol. 22, no. 3, pp. 292-308, Aug. 1999. (Pubitemid 30559649)
12. J. R. Carson, "Wave propagation over parallel wires: The proximity effect," Philosoph. Mag., ser. 6, vol. 41, no. 244, pp. 607-633, Apr. 1921.
13. Ansoft HFSS. Ansoft Corporation, Pittsburgh, PA, 2009. [Online]. Available: http://www.ansoft.com/products/hf/hfss
14. T. Bandyopadhyay, R. Chatterjee, C. Daehyun, M. Swaminathan, and R. Tummala, "Electrical modeling of through silicon and package vias," in Proc. IEEE Int. 3-D System Integration Conf., San Francisco, CA, Sep. 2009, pp. 1-8.
15. N. Arora, MOSFET Modeling for VLSI Simulation-Theory and Practice. Singapore: World Sci., 2007.