FPGA architecture for 2d discrete Fourier transform based on 2d decomposition for large-sized data

Journal of Signal Processing Systems

Volumn 64, Issue 1, 2011, Pages 109-122

  Yu, Chi Li ^a   Kim, Jung Sub ^b   Deng, Lanping ^a   Kestur, Srinidhi ^b   Narayanan, Vijaykrishnan ^b   Chakrabarti, Chaitali ^a  

^a AZ 85281   (United States)

^b The Center for Nanotechnology Education and Utilization   (United States)

Author keywords

Algorithm architecture co design; DFT; Multi dimensional signal processing

Indexed keywords

ACCESS PATTERNS; APPLICATION SPECIFIC; AUTOMATIC SYSTEMS; CO-DESIGNS; DECOMPOSITION ALGORITHM; DFT; DIGITAL IMAGE PROCESSING; EFFICIENT ARCHITECTURE; EXTERNAL MEMORY; FPGA ARCHITECTURES; HIGH THROUGHPUT; INHERENT PARALLELISM; INPUT DATAS; INPUT SIZE; MEMORY BANDWIDTHS; MEMORY CONSTRAINTS; MEMORY INTERFACE; MULTI-DIMENSIONAL SIGNAL PROCESSING; PROPOSED ARCHITECTURES; RECONFIGURABLE PLAT-FORMS; ROW-COLUMN;

ALGORITHMS; BANDWIDTH; DISCRETE FOURIER TRANSFORMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE PROCESSING; METADATA; RECONFIGURABLE HARDWARE; THROUGHPUT;

MEMORY ARCHITECTURE;

EID: 79956369368     PISSN: 19398018     EISSN: 19398115     Source Type: Journal    
DOI: 10.1007/s11265-010-0500-y     Document Type: Article

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