Thermal-aware Steiner routing for 3D stacked ICs

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2007, Pages 205-211

  Pathak, Mohit ^a   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D TREE; COMPUTER-AIDED DESIGN; DEVICE LAYERS; ELMORE DELAY; INTERNATIONAL CONFERENCES; PERFORMANCE CONSTRAINTS; ROUTING PROBLEMS; ROUTING TOPOLOGY; STEINER TREES; THROUGH-VIAS; TREE CONSTRUCTION; TREE CONSTRUCTION ALGORITHMS;

CANNING; CONSTRAINED OPTIMIZATION; DESIGN; MARINE BIOLOGY; OPTIMIZATION; ROUTING ALGORITHMS;

TREES (MATHEMATICS);

EID: 50249181803     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2007.4397267     Document Type: Conference Paper

References (9)

1. M. Yilidiz and P.H.Madded, "Preferred Direction Steiner Trees," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems. 2002.
2. J. Cong and Y. Zhang, "Thermal Via Planning for 3-D ICs," in Proc. IEEE Int. Conf. on Computer-Aided Design, 2005.
3. V. Pavlidis and E. Friedman, "Interconnect Delay Minimization through Interlayer Via Placement in 3-D ICs," in Proc. Great Lakes Symposum on VLSI. 2005.
4. A. Ajami, K. Banerjee, and M. Pedram, "Effects of non-uniform substrate temperature on the clock signal integrity in high performance designs," in Proc. of IEEE Custom Integrated Circuits Conference. May 2001, pp. pp. 233-236.
5. K. Boese, A. Kahng. B. McCoyy, and G. Robins, "Near-Optimal Critical Sink Routing Tree Constructions," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 1995.
6. M. Pathak and S. K. Lim, "Thermal-aware Steiner Routing for 3D Stacked ICs." Georgia Institute of Technology. Tech. Rep. GIT-CERCS-07-18, 2007.
7. T.-Y. Wang and C. C.-P. Chen, "3-d thermal-adi: A linear-time chip level transient thermal simulator," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 1434-1445, 2002.
8. B. Goplen and S. Sapatnekar, "Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach," in Proc. IEEE Int. Conf. on Computer-Aided Design. 2003.
9. J. Cong. K.-S. Leung, and D. Zhou. "Performance Driven Interconnect Design Based on distributed RC delay model," in Proc. ACM Design Automation Conf., 1993.