HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2011, Pages 99-110

  Lee, Sanghoon ^a   Tiwari, Devesh ^a   Solihin, Yan ^a   Tuck, James ^a  

^a North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDRESS SPACE; APPLICATION DOMAINS; CHIP MULTIPROCESSOR; COHERENCE PROTOCOL; CONTEXT SWITCH; FINE-GRAINED PARALLELISM; HARDWARE-ACCELERATED; MULTI-THREADED PROGRAMS; OPERATING SYSTEMS; PARALLELIZATIONS; PROCESSOR CORES; SOFTWARE PIPELINING; VIRTUALIZATIONS;

COMPUTER ARCHITECTURE; COMPUTER SOFTWARE SELECTION AND EVALUATION; COST REDUCTION; DESIGN; HARDWARE; MULTITASKING; QUEUEING THEORY; SOFTWARE RELIABILITY;

COMPUTER HARDWARE;

EID: 79955913755     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2011.5749720     Document Type: Conference Paper

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