A lock-free, cache-efficient multi-core synchronization mechanism for line-rate network traffic monitoring

Proceedings of the 2010 IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2010

Volumn , Issue , 2010, Pages

  Lee, Patrick P C ^a   Bu, Tian ^b   Chandranmenon, Girish ^b  

^a CHINESE UNIVERSITY OF HONG KONG   (Hong Kong)

^b LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BASIC BUILDING BLOCK; CACHE LOCALITY; CACHE-EFFICIENT; CONTROL VARIABLE; DATA ACCESS; DATA TRAFFIC; GENERAL CLASS; INFORMATION PROCESSING CAPABILITY; LINE RATE; LOCK-FREE; MULTI CORE; MULTICORE ARCHITECTURES; MULTITHREADED; NETWORK TRAFFIC; PACKET PROCESSING; PROCESSOR ARCHITECTURES; RUNNING-IN; SYNCHRONIZATION MECHANISMS; THREAD SYNCHRONIZATION; TRACE DRIVEN SIMULATION; TRAFFIC MONITORING;

COMPUTER ARCHITECTURE; CONCURRENCY CONTROL; DATA PROCESSING; DISTRIBUTED PARAMETER NETWORKS; PACKET NETWORKS; SYNCHRONIZATION;

MACHINE DESIGN;

EID: 77953978338     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2010.5470368     Document Type: Conference Paper

References (20)

1. L. Foschini, A. Thapliyal, L. Cavallaro, C. Kruegel, and G. Vigna. A Parallel Architecture for Stateful, High-Speed Intrusion Detection. In Proc. of ICISS, Dec 2008.
2. J. Giacomoni, T. Moseley, and M. Vachharajani. FastFor-ward for Efficient Pipeline Parallelism - A Cache-Optimized Concurrent Lock-Free Queue. In PPoPP, 2008.
3. Intel Corporation. Intel VTune. http://software.intel.com/en-us/intel- vtune/.
4. Intel Corporation. Intel 64 and IA-32 Architectures Optimization Reference Manual, Mar 2009.
5. Intel Corporation. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide, Part 1, Jun 2009.
6. J. Jung, V. Paxson, A. W. Berger, and H. Balakrishnan. Fast Portscan Detection Using Sequential Hypothesis Testing. In IEEE Symp. on Security and Privacy, 2004.
7. C. Kruegel, F. Valeur, G. Vigna, and R. Kemmerer. Stateful Intrusion Detection for High-Speed Networks. In IEEE Symp. on Security and Privacy, May 2002.
8. E. Ladan-Mozes and N. Shavit. An Optimistic Approach to Lock-free FIFO Queues. Distributed Computing, 20:323-341, 2008.
9. L. Lamport. Concurrent Reading and Writing. Communications of the ACM, 20(11), Nov 1977.
10. L. Lamport. Proving the Correctness of Multiprocess Programs. IEEE Trans. on Software Engineering, 3(2), Mar 1977.
11. L. Lamport. How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs. IEEE Trans. on Computers, C-28(9), Sep 1979.
12. V. Paxson, R. Sommer, and N. Weaver. An Architecture for Exploiting Multi-Core Processors to Parallelize Network Intrusion Prevention. In IEEE Sarnoff, 2007.
13. Y. Qi, B. Xu, F. He, B. Yang, J. Yu, and J. Li. Towards High-performance Flow-level Packet Processing on Multi-core Network Processors. In ACM/IEEE ANCS, 2007.
14. L. Schaelicke, K. Wheeler, and C. Freeland. SPANIDS: A Scalable Network Intrusion Detection Loadbalancer. In Proc. of Computing Frontiers (CF), May 2005.
15. W. N. Scherer III, D. Lea, and M. L. Scott. Scalable Synchronous Queues. In PPoPP, 2008.
16. S. Staniford, J. A. Hoagland, and J. M. McAlerney. Practical Automated Detection of Stealthy Portscans. Journal of Computer Security, 10:105-136, 2002.
17. P. Tsigas and Y. Zhang. A Simple, Fast and Scalable Non-blocking Concurrent FIFO Queue for Shared Memory Multiprocessor Systems. In Proc. of ACM SPAA, 2001.
18. J. Wang, H. Cheng, B. Hua, and X. Tang. Practice of Parallelizing Network Applications on Multi-core Architectures. In ISC, 2009.
19. N. Weaver and R. Sommer. Stress Testing Cluster Bro. In DETER workshop, 2007.
20. Q. Wu and T. Wolf. On Runtime Management in Multi-Core Packet Processing Systems. In ACM/IEEE ANCS, 2008.