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Volumn 7640, Issue , 2010, Pages
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Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows
a a a b c b b
c
Synopsys SARL
(France)
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Author keywords
compliance; design rules; double patterning; DPT; dual patterning; performance; scalability
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Indexed keywords
INTEGRATED CIRCUIT LAYOUT;
PROBABILITY DISTRIBUTIONS;
SCALABILITY;
TITRATION;
COMPLIANCE;
DESIGN RULES;
DOUBLE PATTERNING;
DPT;
DUAL PATTERNING;
PERFORMANCE;
GEOMETRY;
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EID: 79955801238
PISSN: 0277786X
EISSN: 1996756X
Source Type: Conference Proceeding
DOI: 10.1117/12.848194 Document Type: Conference Paper |
Times cited : (4)
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References (6)
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