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Volumn 7640, Issue , 2010, Pages

Implementing and validating double patterning in 22-nm to 16-nm product design and patterning flows

Author keywords

compliance; design rules; double patterning; DPT; dual patterning; performance; scalability

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; PROBABILITY DISTRIBUTIONS; SCALABILITY; TITRATION;

EID: 79955801238     PISSN: 0277786X     EISSN: 1996756X     Source Type: Conference Proceeding    
DOI: 10.1117/12.848194     Document Type: Conference Paper
Times cited : (4)

References (6)
  • 1
    • 35148840123 scopus 로고    scopus 로고
    • Patterning design split implementation and validation for the 32nm Node
    • Drapeau, M. Wiaux, V., Hendrickx, E. Verhaegen, and S. Machida, T., "Patterning design split implementation and validation for the 32nm Node" Proc. SPIE 6521, 652109 (2007).
    • (2007) Proc. SPIE , vol.6521 , pp. 652109
    • Drapeau Wiaux, M.V.1    Verhaegen, H.E.2    Machida, T.S.3
  • 4
    • 66749148537 scopus 로고    scopus 로고
    • Large-scale double-patterning compliant layouts for DP engine and design rule
    • Cork, C., Lucas, K., Hapli, H., Raffard H., and Barnes, L., "Large-scale double-patterning compliant layouts for DP engine and design rule" Proc. SPIE 7275, 72751K (2009).
    • (2009) Proc. SPIE 7275
    • Cork, C.1    Lucas, K.2    Hapli, H.3    Raffard, H.4    Barnes, L.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.