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Volumn 7275, Issue , 2009, Pages
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Large-scale double-patterning compliant layouts for DP engine and design rule development
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Author keywords
[No Author keywords available]
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Indexed keywords
ASIC DESIGN;
DESIGN RULES;
DESIGN STAGE;
DIFFERENT SIZES;
DOUBLE PATTERNING;
LARGE DATASETS;
LARGE DESIGNS;
MICRO LEVEL;
MOORE'S LAW;
MULTIPLE LAYERS;
MULTIPLE PROCESSORS;
PHASE-SHIFT MASK;
STANDARD CELL;
APPLICATION SPECIFIC INTEGRATED CIRCUITS;
CELL MEMBRANES;
COLORING;
ELECTRIC BATTERIES;
ELECTRIC POWER SUPPLIES TO APPARATUS;
ENGINES;
EXTREME ULTRAVIOLET LITHOGRAPHY;
INTEGRATED CIRCUITS;
MACHINE DESIGN;
MASKS;
STANDARDS;
REGULATORY COMPLIANCE;
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EID: 66749148537
PISSN: 0277786X
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1117/12.815213 Document Type: Conference Paper |
Times cited : (3)
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References (8)
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