A 16Gb/s 1st-tap FFE and 3-tap DFE in 90nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 162-163

  Sugita, Hideyuki ^a   Sunaga, Kazuhisa ^a   Yamaguchi, Koichi ^a   Mizuno, Masayuki ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; CLOCK TIMING; FEEDBACK DELAY; FEEDBACK OPERATIONS; FEEDBACK PATHS; FEEDFORWARD TECHNIQUE; HIGH-SPEED; HIGH-SPEED CHIPS; HIGH-SPEED OPERATION; KEY COMPONENT; OPERATING SPEED; SAMPLED DATA; SPEED-UPS; VOLTAGE SWINGS; WAVE FORMS;

CMOS INTEGRATED CIRCUITS; DECISION FEEDBACK EQUALIZERS; INTERSYMBOL INTERFERENCE; JITTER; MICROPROCESSOR CHIPS;

SPEED;

EID: 77952234502     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5434005     Document Type: Conference Paper

References (3)

1. nd -Order Data-Filtered CDR," ISSCC Dig. Tech. Papers, pp. 228-229, Feb., 2007.
2. J.F Bulzacchelli, et al., "A 78mW 11.1Gb/s 5-Tap DFE Receiver with Digitally Calibrated Current-Integrating Summers in 65nm CMOS," ISSCC Dig. Tech. Papers, pp. 368-369, Feb., 2009.
3. T.O. Dickson, et al., "A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer with Current-Integrating Summers in 45-nm SOI CMOS Technology," IEEE Symp. VLSI Circuits, pp. 58-59, Jun., 2008.