A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2009, Pages 188-190

  Hidaka, Yasuo ^a   Gai, Weixin ^a   Horie, Takeshi ^b   Jiang, Jian Hong ^a   Koyanagi, Yoichi ^b   Osone, Hideki ^a  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

^b FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 70349285146     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2009.4977371     Document Type: Conference Paper

References (10)

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2. B.S. Leibowitz, J. Kizer, H. Lee, et al., "A 7.5 Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR," ISSCC Dig. Tech. Papers, pp. 228-229, Feb., 2007.
3. M. Harwood, N. Warke, R. Simpson et al., "A 12.5 Gb/s SerDes in 65nm CMOS using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery," ISSCC Dig. Tech. Papers, pp. 436-437, Feb., 2007.
4. K. Fukuda, H. Yamashita, F. Yuki, et al., "An 8Gb/s Transceiver with 3×-Oversampling 2- Threshold Eye-Tracking CDR Circuit for -36.8dB-loss Backplane," ISSCC Dig. Tech. Papers, pp. 98-99, Feb., 2008.
5. K. Krishna, D.A. Yokoyama-Martin, A. Caffee, et al., "A Multigigabit Backplane Transceiver Core in 0.13-μ CMOS With a Power-Efficient Equalization Architecture," IEEE J. Solid-State Circuits, vol.40, no.12, pp. 2658-2666, Dec., 2005.
6. N. Krishnapura, M. Barazande-Pour, Q. Chaudhry, et al., "A 5Gb/s NRZ Transceiver with Adaptive Equalization for Backplane Transmission," ISSCC Dig. Tech. Papers, pp. 60-61, Feb., 2005.
7. S. Dasgupta, C.R. Johnson, Jr., and A.M. Baksho, "Sign-Sign LMS Convergence with Independent Stochastic Inputs," IEEE Trans. Information Theory, vol.36, no.1, pp. 197-201, Jan., 1990.
8. J. W. M. Bergmans, Digital Baseband Transmission and Recording, Chapter 8.5, Kluwer Academic Publishers, 1996.
9. Y. Hidaka, W. Gai, A. Hattori, et al., "A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer," ISSCC Dig. Tech. Papers, pp. 442-443, Feb., 2007.
10. IEEE Std 802.3ap-2007, "Part 3: Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications, Amendment 4: Ethernet Operation over Electrical Backplanes," May, 2007.