A three-terminal dual-pillar STT-MRAM for high-performance robust memory applications

IEEE Transactions on Electron Devices

Volumn 58, Issue 5, 2011, Pages 1508-1516

  Mojumder, Niladri Narayan ^a   Gupta, Sumeet Kumar ^a   Choday, Sri Harsha ^a   Nikonov, Dmitri E ^b   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Magnetic domain walls; magnetic memory; magnetic multilayers; magnetization reversal; memory architecture; nonvolatile memory; spin transfer torque; tunneling magnetoresistance

Indexed keywords

BIT CELL; BIT LINES; CELL STABILITY; CO-OPTIMIZATION; CRITICAL SWITCHING CURRENT; DATA READOUT; DOMAIN WALL MOTION; EFFECTIVE MASS; HIGH-SPEED; LOWER PROBABILITIES; MAGNETIC MEMORY; MAGNETIC RANDOM ACCESS MEMORY CELLS; MAGNETIC TUNNEL JUNCTION; MEMORY APPLICATIONS; MEMORY ARRAY; MEMORY ARRAY ARCHITECTURE; MICROMAGNETIC SIMULATIONS; MULTILAYER STACKS; NON-EQUILIBRIUM GREEN'S FUNCTION FORMALISM; NON-VOLATILE; NON-VOLATILE MEMORIES; PARAMETRIC PROCESS; SELF-ALIGNED; SENSING SCHEMES; SINGLE-ENDED; SPIN-TRANSFER TORQUE; TRANSPORT SIMULATION; TUNNELING MAGNETORESISTANCE; TUNNELING OXIDES;

ARCHITECTURE; CELLS; DOMAIN WALLS; ELECTRIC RESISTANCE; MAGNETIC DOMAINS; MAGNETIC FILMS; MAGNETIC MULTILAYERS; MAGNETIC STORAGE; MAGNETIC STRUCTURE; MAGNETIZATION REVERSAL; MAGNETOELECTRONICS; MAGNETORESISTANCE; MEMORY ARCHITECTURE; TUNNEL JUNCTIONS;

MRAM DEVICES;

EID: 79955546163     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2011.2116024     Document Type: Article

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