Design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 12, 2010, Pages 1710-1723

  Li, Jing ^a   Ndai, Patrick ^a   Goel, Ashish ^a   Salahuddin, Sayeef ^b   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

magnetic ram (MRAM); memory yield; parametric failures; Spin torque transfer (STT)

Indexed keywords

ACCESS TIME; DESIGN CYCLE; DESIGN PARADIGM; DESIGN PARAMETERS; DESIGN REQUIREMENTS; EFFICIENT DESIGNS; EMBEDDED APPLICATION; FAILURE PROBABILITY; HIGH DENSITY; IN-PROCESS PARAMETERS; INTEGRATION DENSITY; LOW COSTS; MAGNETIC RAMS; MEMORY ARRAY; MEMORY TECHNOLOGY; MEMORY YIELD; MRAM TECHNOLOGY; NONVOLATILITY; PARAMETER VARIATION; PARAMETRIC FAILURE; PROCESS VARIATION; READ STABILITY; SPIN TORQUE; STT-MRAM; YIELD ENHANCEMENT;

DESIGN; DYNAMIC RANDOM ACCESS STORAGE; FLASH MEMORY; STATIC RANDOM ACCESS STORAGE; TORQUE;

MAGNETIC STORAGE;

EID: 78649493955     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2027907     Document Type: Article

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