Low-power, resilient interconnection with orthogonal latin squares

IEEE Design and Test of Computers

Volumn 28, Issue 2, 2011, Pages 30-38

  Lee, Seung Eun ^a   Wu, Wei ^b   Iyer, Ravi ^b   Yang, Yoon Seok ^c   Choi, Gwan S ^c  

^a Seoul National University of Science and Technology   (South Korea)

^b INTEL CORPORATION   (United States)

^c TEXAS A AND M UNIVERSITY   (United States)

Author keywords

design and test; ECC; error correcting code; OLSC; on chip interconnection; orthogonal Latin square; resilience and low power design

Indexed keywords

DESIGN AND TESTS; ECC; ERROR-CORRECTING CODE; OLSC; ON-CHIP INTERCONNECTION; ORTHOGONAL LATIN SQUARES; RESILIENCE AND LOW POWER DESIGN;

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY UTILIZATION; INFORMATION THEORY; INTERCONNECTION NETWORKS; SIGNALING;

DESIGN;

EID: 79953654204     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2011.35     Document Type: Article

References (6)

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