200 mm silicon on porous layer substrates made by the smart cut technology for double layer-transfer applications

Journal of the Electrochemical Society

Volumn 158, Issue 5, 2011, Pages

  Stragier, A S ^a   Signamarcheix, T ^a   Salvetat, T ^a   Nolot, E ^a   Dechamp, J ^a   Mercier, D ^a   Gergaud, P ^a   Tauzin, A ^a   Clavelier, L ^a   Lemiti, M ^b  

^a CEA LETI   (France)

^b INSTITUT DES NANOTECHNOLOGIES DE LYON   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING TEMPERATURES; BI-LAYER; CRYSTALLINITIES; DEVICE INTEGRATION; DOUBLE LAYERS; HIGH QUALITY; POROUS LAYERS; POROUS SI; POROUS SILICON LAYERS; SI FILMS; SI LAYER; SILICON SUBSTRATES; SILICON-ON-INSULATORS; SINGLE-CRYSTALLINE; SMART CUT TECHNOLOGY; STRUCTURAL AND MECHANICAL PROPERTIES; STRUCTURE FABRICATION; WHOLE PROCESS;

CRYSTALLINE MATERIALS; FABRICATION; MECHANICAL PROPERTIES; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; SUBSTRATES; WAFER BONDING;

POROUS SILICON;

EID: 79953208643     PISSN: 00134651     EISSN: None     Source Type: Journal    
DOI: 10.1149/1.3568947     Document Type: Article

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