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Volumn 33, Issue 4, 2010, Pages 509-517
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Wafer bonding process selection
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Author keywords
[No Author keywords available]
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Indexed keywords
ELECTRONICS PACKAGING;
PRODUCT DESIGN;
SILICON WAFERS;
3-D INTERCONNECTS;
ADVANCED PACKAGING;
BONDING PROCESS;
MEMSDEVICES;
WAFER BONDING PROCESS;
WAFER LEVEL;
WAFER BONDING;
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EID: 79952645871
PISSN: 19385862
EISSN: 19386737
Source Type: Conference Proceeding
DOI: 10.1149/1.3483542 Document Type: Conference Paper |
Times cited : (6)
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References (10)
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