Nano-CMOS mixed-signal circuit metamodeling techniques: A comparative study

Proceedings - 2010 International Symposium on Electronic System Design, ISED 2010

Volumn , Issue , 2010, Pages 191-196

  Garitselov, Oleg ^a   Mohanty, Saraju P ^a   Kougianos, Elias ^a   Patra, Priyadarsan ^b  

^a UNIVERSITY OF NORTH TEXAS   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Circuit simulation; Metmodeling; Mixed signal circuits; Nanoscale CMOS; Statistical sampling

Indexed keywords

45NM TECHNOLOGY; CIRCUIT DESIGNS; COMPARATIVE STUDIES; DESIGN PROCESS; DESIGN SPACE EXPLORATION; DESIGN SPACES; DESIGN TIME; FREQUENCY OF OSCILLATION; LATIN HYPERCUBE SAMPLING; META MODEL; META-MODELING TECHNIQUE; METMODELING; MIXED-SIGNAL CIRCUITS; MONTE CARLO; NANO CMOS; NANOSCALE CMOS; NUMBER OF SAMPLES; PARASITICS; PERFORMANCE METRICS; RING OSCILLATOR; SAMPLING TECHNIQUE; SPICE SIMULATIONS; STATISTICAL SAMPLING; TIME CONSTRAINTS;

CIRCUIT SIMULATION; DESIGN OF EXPERIMENTS; ELECTRONICS ENGINEERING; INTEGRATED CIRCUIT MANUFACTURE; MONTE CARLO METHODS; NANOSTRUCTURED MATERIALS; OSCILLATORS (ELECTRONIC); SPACE RESEARCH; SYSTEMS ANALYSIS;

SAMPLING;

EID: 79952569041     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISED.2010.44     Document Type: Conference Paper

References (13)

1. J. Park, K. Choi, and D. J. Allstot, "Parasitic-aware design and optimization of a fully integrated CMOS wideband amplifier," in Proc. of the Asia South Pacific Design Automation Conference, 2003, pp. 904-907.
2. D. Ghai, S. P. Mohanty, and E. Kougianos, "Design of parasitic and process-variation aware nano-CMOS RF circuits: A VCO case study," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 9, pp. 1339-1342, September 2009.
3. T. J. Santner, B. J. Williams, and W. I. Notz, The Design and Analysis of Computer Experiments. New York: Springer, 2003.
4. K.-T. Fang, R. Li, and A. Sudjianto, Design and Modeling for Computer Experiments. London: Chapman & Hall/CRC, 2006.
5. A. Lamecki and M. Mrozowski, "Design of integrated inductors using parameterized surrogate models," in Proc. of the International Conference on Computer as a Tool (EUROCON), 2007, pp. 102-105.
6. A. Lamecki, L. Balewski, and M. Mrozowski, "Towards automated full-wave design of microwave circuits," in Proc. 17th International Conf. Microwaves, Radar and Wireless Communications, 2008, pp. 1-2.
7. R. Samanta, J. Hu, and P. Li, "Discrete buffer and wire sizing for link-based non-tree clock networks," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 7, pp. 1025-1035, July 2010.
8. J. L. Wong, A. Davoodi, A. Khanderwal, A. Srivastava, and M. Potkonjak, "A statistical methodology for wire-length prediction," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 7, pp. 1327-1336, July 2006. (Pubitemid 43824525)
9. J. L. Wong, A. Davoodi, A. Khanderwal, A. Srivastava, and M. Potkonjak, "Statistical timing analysis using kernel smoothing," in 25th International Conference on Computer Design (ICCD), 2007, pp. 97-102.
10. J. A. McNeill and D. Ricketts, The Designer's Guide to Jitter in Ring Oscillators. New York: Springer, 2009.
11. L. C. Rodoni, F. Ellinger, and H. Jackel, "Ultrafast CMOS inverter with 4.7 ps gate delay fabricated on 90nm SOI technology," Electronic Letters, vol. 40, no. 20, pp. 1251-1252, Sept. 2004.
12. T. C. Weigandt, B. Kim, and P. R. Gray, "Analysis of timing jitter in CMOS ring oscillators," in Proc. Int. Symp. Circuits Systems, June 1994, pp. 4.27-4.30.
13. S. Kang and Y. Leblebici, CMOS Digital Inegrated Circuits, 3rd ed. New York: McGraw Hill, 2003.