Design of parasitic and process-variation aware Nano-CMOS RF circuits: A VCO case study

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 9, 2009, Pages 1339-1342

  Ghai, Dhruva ^a   Mohanty, Saraju P ^a   Kougianos, Elias ^a  

^a UNIVERSITY OF NORTH TEXAS   (United States)

Author keywords

Monte Carlo; Nano CMOS; Process variation

Indexed keywords

AREA OVERHEAD; COMBINED EFFECT; CURRENT STARVED; DESIGN CYCLE; DESIGN FLOWS; DESIGN ITERATION; MONTE CARLO; MONTE CARLO SIMULATION; NANO-CMOS; NETLIST; OBJECTIVE OPTIMIZATION; OSCILLATION FREQUENCY; PARASITICS; PERFORMANCE DEGRADATION; PROCESS VARIATION; RADIO FREQUENCY INTEGRATED CIRCUITS; VOLTAGE CONTROLLED OSCILLATOR;

COMPUTER SIMULATION LANGUAGES; CONSTRAINED OPTIMIZATION; ELECTRIC POTENTIAL; INTEGRATED CIRCUITS; MONTE CARLO METHODS; RESEARCH; VARIABLE FREQUENCY OSCILLATORS;

DESIGN;

EID: 69649095108     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2002046     Document Type: Article

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