A highly manufacturable integration technology for 27nm 2 and 3bit/cell NAND flash memory

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2010, Pages

  Lee, Choong Ho ^a   Sung, Suk Kang ^a   Jang, Donghoon ^a   Lee, Sehoon ^a   Choi, Seungwook ^a   Kim, Jonghyuk ^a   Park, Sejun ^a   Song, Minsung ^a   Baek, Hyun Chul ^a   Ahn, Eungjin ^a   Shin, Jinhyun ^a   Shin, Kwangshik ^a   Min, Kyunghoon ^a   Cho, Sung Soon ^a   Kang, Chang Jin ^c   Choi, Jungdal ^b   Kim, Keonsoo ^a   Choi, Jeong Hyuk ^a   Suh, Kang Deog ^d   Jung, Tae Sung ^a  

^a Flash Development Center   (South Korea)

^b Flash Core Technology Lab   (South Korea)

^c Process Development Team Semiconductor R and D Center Samsung Electronics Co   (South Korea)

^d Sungkyunkwan University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

3-BIT PER CELL; CELL OPERATION; CHANNEL DOPINGS; CHANNEL JUNCTIONS; DESIGN RULES; DOPING STRUCTURES; DOUBLE PATTERNING; FLASH CELL; INTEGRATION TECHNOLOGIES; MULTI-LEVEL; NAND FLASH MEMORY; SELF-ALIGNED; UNIT CELL SIZE;

ELECTRON DEVICES; NAND CIRCUITS;

FLASH MEMORY;

EID: 79951832474     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2010.5703299     Document Type: Conference Paper

References (7)

1. D. Kwak et al., "Integration Technology of 30nm Generation Multi-Level NAND Flash for 64Gb NAND Flash Memory," in VLSI Tech. Dig., 2007, pp. 12-13.
2. J.A. Kittl, A. Veloso, A. Lauwers, K.G. Anil, C. Demeurisse, S. Kubicek, M. Niwa, M.J.H. van Dal, O. Richard, M.A. Pawlak, M. Jurczak, C. Vrancken, T. Chiarella, S. Brus, K. Maex and S. Biesemans, "Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths," in VLSI Tech. Dig., 2005, pp. 72-73.
3. 2) NAND flash technology using Super-Shallow Channel Profile (SSCP) engineering," in IEDM Tech. Dig., 2000, pp. 775-778.
4. J. Kim; S. Ahn, "Improvement of the tunnel oxide quality by a low thermal budget dual oxidation for flash memories," IEEE Electron Device Lett, vol 18, no 8, pp. 385-387, 1997.
5. C. Lee, J. Choi, Y. Park, C. Kang, B. Choi, H. Kim, H. Oh and W. Lee, "Highly scalable NAND flash memory with robust immunity to program disturbance using symmetric inversion-type source and drain structure," in VLSI Tech. Dig., 2008, pp. 118-119.
6. J.-D. Lee, S.-H. Hur and J.-D. Choi, "Effect of floating-gate interference on NAND flash memory cell operation," IEEE Electron Device Letters, vol. 23, no. 5, pp264-266, May 2002.
7. D. Kang, S. Jang, K. Lee, J. Kim, H. Kwon, W. Lee, B. G. Park, J.D. Lee, and H. C. Shin,"Improving the Cell Characteristics Using Low-k Gate Spacer in 1Gb NAND Flash Memory," IEEE Nonvolatile Semiconductor Memory Workshop, 2006, p.36.