Synthesis of floating-point addition clusters on FPGAs using carry-save arithmetic

Proceedings - 2010 International Conference on Field Programmable Logic and Applications, FPL 2010

Volumn , Issue , 2010, Pages 19-24

  Verma, Amit ^a   Verma, Ajay K ^b   Parandeh Afshar, Hadi ^b   Brisk, Philip ^c   Ienne, Paolo ^b  

^a NATIONAL INSTITUTE OF TECHNOLOGY   (India)

^b EPFL   (Switzerland)

^c University of California Riverside   (United States)

Author keywords

Carry save arithmetic; Floating point addition; FPGA

Indexed keywords

CARRY-SAVE; CRITICAL PATH DELAYS; DATA PATHS; FLOATING-POINT ADDITION; FLOATING-POINT DATA; FPGA;

DIGITAL ARITHMETIC; PROGRAM COMPILERS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 79951755290     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2010.15     Document Type: Conference Paper

References (8)

1. M. Langhammer, "Floating-point Datapath Synthesis for FPGAs," Proc. Intl. Conf. Field Programmable Logic and Applications (FPL '08), pp. 355-360, Sept. 2008.
2. M. Langhammer and T. VanCourt, "FPGA Floating-point Datapath Compiler," Proc. IEEE Symp. Field-Programmable Custom Computing Machines (FCCM '09), Apr. 2009.
3. H. Parandeh-Afshar, P. Brisk, and P. Ienne, "Exploiting Fast Carry-Chains of FPGAs for Designing Compressor Trees," Proc. Intl. Conf. Field Programmable Logic and Applications (FPL '09), Aug.-Sept. 2009.
4. P.-M. Seidel and G. Even, "Delay-Optimized Implementation of IEEE Floating-Point Addition," IEEE Trans. Computers, vol. 53, no. 2, pp. 97-113, February, 2004.
5. A. K. Verma, P. Brisk, and P. Ienne, "Iterative Layering: Optimizing Arithmetic Circuits by Structing the Information Flow," Proc. Intl. Conf. Computer-Aided Design (ICCAD '09), Nov. 2009.
6. th IEEE Intl. Symp. Computer Arithmetic (ARITH-19 '09), pp. 161-168, June, 2009.
7. F. de Dinechin, C. Klein, and B. Pasca, "Generating High-Performance Custom Floating-Point Pipeline," Proc. Intl. Conf. Field Programmable Logic and Applications (FPL '09), Aug.-Sept. 2009, and Technical Report LIP-2009-16, Ens-Lyon, Lyon, France, April, 2009.
8. N. Kapre and A. DeHon, "Optimistic Parallelization of Floating-Point Accumulation." Proc. IEEE Symp. Computer Arithmetic (ARITH-18 '07), pp. 205-216, June, 2007.