Multi-operand floating-point addition

Proceedings - Symposium on Computer Arithmetic

Volumn , Issue , 2009, Pages 161-168

  Tenca, Alexandre F ^a  

^a SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FLOATING-POINT ADDITION;

DIGITAL ARITHMETIC;

ADDERS;

EID: 70350787064     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ARITH.2009.27     Document Type: Conference Paper

References (7)

1. J. Bruguera and T. Lang. Floating-point fused multiply-add: reduced latency for floating-point addition. In 17th IEEE Symposium on Computer Arithmetic, pages 42-51, 2005.
2. M. D. Ercegovac and T. Lang. Digital Arithmetic. Morgan Kaufmann, 2003.
3. D. Goldberg. What Every Computer Scientist Should Know About Floating-Point Arithmetic. ACM Computing Surveys, March 1991.
4. IEEE Std 754-1985. IEEE Standard for Binary Floating-Point Arithmetic. IEEE, 1985.
5. N. Kapre and A. DeHon. Optimistic Parallelization of Floating-Point Accumulation. In 18th IEEE Symposium on Computer Arithmetic, pages 205 - 216, 2007.
6. B. Parhami. Computer Arithmetic: Algorithms and Hardware Designs. Oxford, 2000.
7. P.-M. Seidel and G. Even. Delay-optimized implementation of IEEE floating-point addition. IEEE Transactions on Computers, 49(7):638-650, July 2000.