A new IDDQ testing scheme employing charge storage BICS circuit for deep submicron CMOS ULSI

Proceeding - 1998 IEEE International Workshop on IDDQ Testing, IDDQ 1998

Volumn 1998-November, Issue , 1998, Pages

  Lu, Chih Wen ^a   Lee, Chung Len ^a   Chen, Jwu E ^b   Su, Chauchin ^c  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b CHUNG HUA UNIVERSITY   (Taiwan)

^c NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

LOW POWER ELECTRONICS; TIMING CIRCUITS; ULSI CIRCUITS;

CHARGE STORAGE; CIRCUIT PARTITIONING; DEEP SUB-MICRON; DEEP SUBMICRON CMOS; DIAGNOSABILITY; HIGH RESOLUTION; INPUT VOLTAGES; LOW POWER SUPPLY VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 79951684156     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IDDQ.1998.730757     Document Type: Conference Paper

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