Hierarchical routing architectures in clustered 2D-mesh networks-on-chip

2010 International SoC Design Conference, ISOCC 2010

Volumn , Issue , 2010, Pages 388-391

  Winter, Markus ^a   Prusseit, Steffen ^a   Fettweis, Gerhard P ^a  

^a DRESDEN UNIVERSITY OF TECHNOLOGY   (Germany)

Author keywords

2D mesh; Cluster; Hierarchical routing; Network on Chip

Indexed keywords

2D-MESH; BANDWIDTH DEGRADATION; CLUSTER; CYCLE-ACCURATE SIMULATION; HIERARCHICAL ROUTING; HIERARCHICAL ROUTINGS; MESH NETWORK; MULTIPROCESSOR-SYSTEM; NETWORK ON CHIP; NETWORKS ON CHIPS; SUITABLE SOLUTIONS;

MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; PROGRAMMABLE LOGIC CONTROLLERS; SERVERS; VLSI CIRCUITS;

MESH NETWORKING;

EID: 79851471036     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCDC.2010.5682890     Document Type: Conference Paper

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