A low-power, high-speed DCT architecture for image compression: Principle and implementation

Proceedings of the 2010 18th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2010

Volumn , Issue , 2010, Pages 304-309

  Jridi, M ^a   Alfalou, A ^a  

^a Laboratoire L at bISEN   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CANONICAL SIGNED DIGITS; CLOCK FREQUENCY; COMMON SUBEXPRESSION ELIMINATION; COMPRESSION METHODS; CONSTANT MULTIPLIERS; DCT ALGORITHMS; DCT COEFFICIENTS; DYNAMIC POWER; FPGA IMPLEMENTATIONS; HIGH-SPEED; LOW POWER; MATERIAL COMPLEXITY; NEW DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COSINE TRANSFORMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE COMPRESSION; MATHEMATICAL OPERATORS; OPTIMIZATION; PROGRAMMABLE LOGIC CONTROLLERS;

DISCRETE COSINE TRANSFORMS;

EID: 78650940212     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2010.5642678     Document Type: Conference Paper

References (23)

1. S. Hauck and A. DeHon, Reconfigurable computing: the theory and practice of FPGA-based computation, ISBN 987-0-12-370522-8, Elsvier Inc 2008.
2. E. Monmasson and M. N. Cirstea, FPGA Design Methodology for Industrial Control SystemsA Review, IEEE Transactions on industrial electronics, Vol. 54, No. 4, pp. 1824-1842, August 2007.
3. M.W. James, An Evaluation of the Suitability of FPGAs for Embedded Vision Systems, CVPR '05: Proceedings of the 2005 IEEE Computer Society Conference on Computer Vision and Pattern Recognition, Washington, DC, USA, pp. 131-137, 2005.
4. ISO/IEC DIS 10 918-1, Digital compression and coding of continuoustone still image, 1992.
5. ISO/IEC JTC1/SC2/WG11, MPEG 90/176, Coding of moving picture and associated audio, 1990.
6. K. F Blinn, What's the deal with the DCT?, IEEE Computer Graphics and Applications, pp. 78-83, July 1993.
7. A. Alfalou, M. Elbouz, M. Jridi and A. Loussert, A new simultaneous compression and encryption method for images suitable to optical correlation, Optics and Photonics for Counterterrorism and Crime Fighting V, edited by Colin Lewis, Proc. of SPIE Vol. 7486, 74860J-1-8, 2009.
8. A.Alfalou and C. Brosseau, Optical image compression and encryption methods, Adv. Opt. Photon. 1, 589-636 (2009).
9. C. Loeffler and A. Lightenberg and G.S. Moschytz , Practical fast 1-D DCT algorithm with 11 multiplication, IEEE, ICAPSS, pp. 988-991, May 1989.
10. P. Duhamel and H. H'mida, New 2n DCT algorithm suitable for VLSI implementation, IEEE, ICAPSS, pp. 1805-1808, November 1987.
11. A. Avizienis Signed-Digit Number Representations for Fast Parallel Arithmetic, IRE Transaction on Electron. Computer, Vol. EC-10, pp. 389-400, 1961.
12. R. Seegal, The canonical signed digit code structure for FIR filters,IEEE Transactions on Acoustics, Speech and Signal Processing, Vol. 28, No. 5, pp. 590-592, 1980.
13. R.I. Hartley, Subexpression sharing in filters using canonic signed digit multipliers,IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 43, No. 10, pp. 677-688 October 1996.
14. C.Y Pai, W.E. Lynch and A.J. Al-Khalili, Low-Power data-dependant 8x8 DCT/IDCT for video compression, IEE, Proceedings. Vision, Image and Signal Processing, Vol. 150, pp. 245-254, August 2003.
15. D. Slawecki and W. Li, DCT/IDCT processor design for high data rate image coding, IEEE Transactions on Circuits and Systems for Video Technology, Vol. 2, No.2, pp, 135-146, Jun 1992.
16. S. Yu and E.E. Swartzlander Jr, DCT implementation with distributed arithmetic, IEEE Transactions on Computers, Vol. 50, No.9, pp, 985-991, September 2001.
17. S.A White, Application of distributed arithmetic to digital signal processing: a tutorial review, IEEE ASSP Magazine,pp, 4-19, July 1989.
18. K. Rao and P. Yip, Discrete cosine transform algorithms advantages applications, Academic Press, New York, 1990.
19. A. Alkholidi, A. Alfalou and H. Hamam, A new approach for optical colored image compression using the JPEG standards, Journal of signal processing, Vol. 87, No. 4, pp. 569-583, April 2007.
20. M. Jridi and A. Alfalou, A VLSI implementation of a new simultaneous images compression and encryption method, to appear in IEEE Imaging Systems and Techniques.
21. Y. Mitsuru and N. Akinori, A high-speed FIR digital filter with CSD coefficients implemented on FPGA,ASP-DAC '01: Proceedings of the 2001 Asia and South Pacific Design Automation Conference, pp. 7-8, 2001.
22. M. Matsui, H. Hara, K. Seta, Y. Uetani, L.S. Klim, T. Nagamatsu and T. Sakura, 200 MHz video compression macrocelles using low-swing differential logic, Proceedings of ISSCC, pp. 76-77, 1994.
23. T. Xanthopoulos, Low power data-dependent transform and still image coding, PhD Thesis, MIT, February 1999.