High-speed FIR digital filter with CSD coefficients implemented on FPGA

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 7-8

  Yamada, M ^a   Nishihara, A ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

Added delay; Adders; Digital filters; Electronic mail; Field programmable gate arrays; Finite impulse response filter; Logic; Pipeline processing; Propagation delay; Table lookup

Indexed keywords

ADDERS; COMPUTER AIDED DESIGN; DIGITAL FILTERS; ELECTRONIC MAIL; ELECTRONIC MAIL FILTERS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); FLOW GRAPHS; IMPULSE RESPONSE; PIPELINES; SIGNAL FLOW GRAPHS; TABLE LOOKUP;

ADDED DELAY; CANONIC SIGNED DIGIT; EQUIVALENT TRANSFORMATIONS; FIR DIGITAL FILTERS; LOGIC; PIPELINE PROCESSING; PROPAGATION DELAYS; SAMPLING FREQUENCIES;

FIR FILTERS;

EID: 84949741726     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913262     Document Type: Conference Paper

References (2)

1. R. Jain, P. T. Yang and T. Yoshino, "FIRGEN: A Computer-Aided Design System for High Performance FIR Filter Integrated Circuits", IEEE Trans. Signal Processing, vol. 39, No7, pp. 1655-1668, July 1991.
2. M. Yamada, A. Nishihara, "Design of FIR Digital Filters with CSD Coefficients Having Power-of-Two DC gain", Technical Report of IEICE, DSP99-145 (1999-12), pp. 99-105, Sept. 1999.