Demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications

IEEE Journal of Solid-State Circuits

Volumn 46, Issue 1, 2011, Pages 308-320

  Spencer, Matthew ^a   Chen, Fred ^b   Wang, Cheng C ^c   Nathanael, Rhesa ^a   Fariborzi, Hossein ^b   Gupta, Abhinav ^a   Kam, Hei ^a   Pott, Vincent ^a   Jeon, Jaeseok ^a   Liu, Tsu Jae King ^a   Marković, Dejan ^c   Alon, Elad ^a   Stojanović, Vladimir ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Adders; digital circuits; MEM relays; microelectromechanical devices; minimum energy point; very large scale integration

Indexed keywords

90 NM TECHNOLOGY NODE; CIRCUIT DESIGN TECHNIQUES; ELECTROMECHANICAL MODELS; MEASURED RESULTS; MECHANICAL CHARACTERISTICS; MICRO-ELECTRO-MECHANICAL; MINIMUM ENERGY POINT; RELAY CIRCUIT; SINGLE-BIT; TEST CHIPS; VERY-LARGE-SCALE INTEGRATION; VLSI SYSTEM;

DIGITAL DEVICES; DIGITAL INTEGRATED CIRCUITS; ENERGY EFFICIENCY; INTEGRATED CIRCUIT MANUFACTURE; MICROELECTROMECHANICAL DEVICES; NETWORK ROUTING; OPTIMIZATION; VLSI CIRCUITS;

ADDERS;

EID: 78650907088     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2074370     Document Type: Conference Paper

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