A 90-nm power optimization methodology with application to the ARM 1136JF-S microprocessor

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 8, 2006, Pages 1707-1716

  Khan, Aurangzeb ^a,b   Watson, Philip ^c   Kuo, George ^b   Le, Due ^b   Nguyen, Trung ^b   Yang, Steven ^b   Bennett, Peter ^b   Huang, Pokai ^b   Gill, Jaspal ^b   Hawkins, Chris ^d   Goodenough, John ^c   Wang, Demin ^b   Ahmed, Irfan ^b   Tran, Peter ^b   Mak, Helder ^b   Kim, Oanh ^b   Martin, Frank ^b   Fan, Yimu ^b   Ge, David ^b   Kung, Joseph ^a,b   Shek, Vincent ^b   more..

^a IEEE   (United States)

^b CADENCE DESIGN SYSTEMS   (United States)

^c ARM LTD   (United Kingdom)

^d ARM Inc   (United States)

Author keywords

Circuit synthesis; Design automation; Design methodology; Digital systems; Electronics industry; Integrated circuit design; Integrated circuit manufacture; Power distribution control

Indexed keywords

CIRCUIT SYNTHESIS; DESIGN AUTOMATION; DESIGN METHODOLOGY; DIGITAL SYSTEMS; INTEGRATED CIRCUIT DESIGN; POWER DISTRIBUTION CONTROL;

CMOS INTEGRATED CIRCUITS; ELECTRONICS INDUSTRY; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; LEAKAGE CURRENTS; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; OPTIMIZATION; RESPONSE TIME (COMPUTER SYSTEMS);

ELECTRIC POWER UTILIZATION;

EID: 33746881766     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.877248     Document Type: Conference Paper

References (8)

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