A silicon MEMS structure for characterization of femto-farad-level capacitive sensors with lock-in architecture

Journal of Micromechanics and Microengineering

Volumn 20, Issue 6, 2010, Pages

  Wei, J ^a   Yue, C ^a,b   Chen, Z L ^b   Liu, Z W ^b   Sarro, P M ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BULK- MICROMACHINING; CAPACITANCE VARIATION; CAPACITIVE SENSOR; CAPACITIVE STRUCTURE; DETECTION LIMITS; FABRICATED DEVICE; INTERMEDIATE LAYERS; LOCK-IN; PERFORMANCE MEASUREMENTS; SILICON MEMS; SINGLE-MASK; TEST METHODOLOGY;

MICROMACHINING; SENSORS;

CAPACITANCE;

EID: 78650871453     PISSN: 09601317     EISSN: 13616439     Source Type: Journal    
DOI: 10.1088/0960-1317/20/6/064019     Document Type: Article

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