Wide-range fast-lock duty-cycle corrector with offset-tolerant duty-cycle detection scheme for 54nm 7GB/s GDDR5 DRAM interface

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2009, Pages 138-139

  Shin, Dongsuk ^a   Na, Kwang Jin ^a   Kwon, Daehan ^a   Kang, Jong Ho ^a   Song, Taeksang ^a   Jung, Ho Don ^a   Lee, Woo Young ^a   Park, Ki Chon ^a   Park, Jung Hoon ^a   Joo, Yong Suk ^a   Cha, Jae Hoon ^a   Jung, Youngho ^a   Kim, Youngran ^a   Han, Donghoon ^a   Choi, Byoung Jin ^a   Lee, Geun Il ^a   Cho, Joo Hwan ^a   Choi, Young Jung ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY SEARCH; DUTY CYCLES; LOCK TIME; SPEED INTERFACES; SUPPLY VOLTAGES; WIDE FREQUENCY RANGE;

DYNAMIC RANDOM ACCESS STORAGE; MICROWAVE ANTENNAS;

VLSI CIRCUITS;

EID: 70449337578     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. K. Kim, et al., "A 5.2Gb/p/s GDDR5 SDRAM with CML Clock Distribution Network," ESSCIRC, pp. 194-197, Sep. 2008.
2. W.-J. Yun, et al., "A 0.1-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology," ISSCC, pp. 21-22, Feb. 2008.
3. S.-J. Bae, et al., "An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion," IEEE JSSC, Vol 43, Jan. 2008, pp. 121-131.
4. 2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC," ISSCC, pp. 184-185, Feb. 2007.