SRAM dedicated PCMs for leakage characterization in nanometer CMOS technologies

Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006

Volumn , Issue , 2006, Pages 316-321

  Léomant, Sylvain ^a   Turier, Arnaud ^b   Ben Ammar, Lotfi ^b   Amara, Amara ^a  

^a ISEP   (France)

^b ATMEL   (France)

Author keywords

Leakage; Methodology; Process control monitor; SRAM

Indexed keywords

CMOS INTEGRATED CIRCUITS; LEAKAGE (FLUID); LEAKAGE CURRENTS; NANOTECHNOLOGY; STATIC RANDOM ACCESS STORAGE;

CMOS TECHNOLOGY; DIFFERENT STRUCTURE; JUNCTION LEAKAGES; LEAKAGE CHARACTERIZATION; MEASUREMENT METHODOLOGY; METHODOLOGY; NANOMETER TECHNOLOGY; NEW TECHNOLOGY DEVELOPMENT;

PROCESS CONTROL;

EID: 78650368799     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dtis.2006.1708680     Document Type: Conference Paper

References (10)

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