Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2010, Pages

  Van Der Plas, Geert ^a   Thijs, Steven ^a   Linten, Dimitri ^a   Katti, Guruprasad ^a   Limaye, Paresh ^a   Mercha, Abdelkarim ^a   Stucchi, Michele ^a   Oprins, Herman ^a   Vandevelde, Bart ^a   Minas, Nikolas ^a   Cupac, Miro ^a   Dehan, Morin ^a   Nelis, Marc ^a   Agarwal, Rahul ^a   Dehaene, Wim ^a   Travaly, Youssef ^a   Beyne, Eric ^a   Marchal, Paul ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP PACKAGES; CMOS TECHNOLOGY; CO-DESIGN FLOW; DESIGN CHALLENGES; ELECTRICAL YIELD; EXPERIMENTAL CHARACTERIZATION; MECHANICAL BEHAVIOR; NEW DESIGN; THERMO-MECHANICAL; THERMOMECHANICAL SIMULATION;

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; THERMOMECHANICAL TREATMENT; THREE DIMENSIONAL;

DESIGN;

EID: 78649879384     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2010.5617425     Document Type: Conference Paper

References (10)

1. S. Gu et al., "Stackable memory of 3D chip integration for mobile applications," IEDM '08.
2. U. Kang, et al., "8Gb 3D DDR3 DRAM Using Through-Silicon-Via Technology," ISSCC 09, paper 07.2.
3. H. Yoshikawa et al., "Chip-Scale Camera Module (CSCM) Using Through-Silicon-Via (TSV)," ISSCC 09, paper 28.5.
4. Y. Suntharalingam et al., "A 4-Side Tileable Back-Illuminated 3D-Integrated Mpixel CMOS Image Sensor," ISSCC 09, paper 02.1.
5. K. Ishida et al., "A 1.8V 30nJ Adaptive Program-Voltage (20V) Generator for 3D-Integrated NAND Flash SSD," ISSCC 09, paper 13.5.
6. J. Van Olmen et al., "3D stacked IC demonstration using a through Silicon Via First approach," Proc. IEDM 2008, pp.303-306.
7. A. Jourdain et al., "Electrically yielding Collective Hybrid Bonding for 3D stacking of ICs," Proc. ECTC 2009, pp. 11-13.
8. G. Van der Plas et al., "Design Issues and Considerations for Low-Cost 3D TSV IC Technology," ISSCC 2010, paper 7.8, pp 148-149.
9. R. Radojcic, et al., "Design for Manufacturability for Fabless Manufacturers," IEEE Solid-State Circuits Magazine, vol. 1, no. 3, pp. 25-33, summer 2009.
10. C. Torregiani et al.," Compact thermal modeling of hot spots in advanced 3D-stacked structures", Proc. EPTC 2009, pp. 131-136