Investigation of charge loss mechanisms in planar and raised STI charge trapping flash memories

International Conference on Simulation of Semiconductor Processes and Devices, SISPAD

Volumn , Issue , 2010, Pages 233-236

  Xia, Zhiliang ^a   Kim, Dae Sin ^a   Lee, Ju Yul ^a   Lee, Keun Ho ^a   Park, Young Kwan ^a   Yoo, Moon Hyun ^a   Chung, Chilhee ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCKING LAYERS; CHARGE LOSS; CHARGE STORAGE; COMPREHENSIVE SIMULATIONS; EXPERIMENTAL DATA; GATE STACKS; HIGH TEMPERATURE; LATERAL SPREADING; MEASUREMENT DATA; NARROW WIDTH; NONUNIFORM; POOLE-FRENKEL EFFECT;

CHARGE TRAPPING; FLASH MEMORY; SILICON NITRIDE;

SEMICONDUCTOR DEVICES;

EID: 78649567677     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SISPAD.2010.5604520     Document Type: Conference Paper

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