Three-dimensional chip stack with integrated decoupling capacitors and thru-si via interconnects

IEEE Electron Device Letters

Volumn 31, Issue 12, 2010, Pages 1461-1463

  Dang, Bing ^a   Shapiro, Michael ^b   Andry, Paul ^a   Tsang, Cornelia ^a   Sprogis, Edmund ^b   Wright, Steven ^a   Interrante, Mario ^b   Griffith, Jonathan ^b   Truong, Van ^b   Guerin, Luc ^b   Liptak, Roger ^b   Berger, Daniel ^b   Knickerbocker, John ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

3 D integration; Chip stack; integrated decoupling capacitors; thru Si via (TSV)

Indexed keywords

3-D INTEGRATION; CAPACITANCE DENSITY; CHIP STACK; CMOS COMPATIBLE; CMOS TEST CHIP; DECOUPLING CAPACITOR; MULTILAYER STACKING; RELIABILITY TEST; THRU-SI VIA (TSV); TWO LAYERS;

CAPACITORS; THREE DIMENSIONAL;

SILICON;

EID: 78649449630     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2010.2084068     Document Type: Article

References (6)

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