Reliable through silicon vias for 3D silicon applications

Proceedings of the 2009 IEEE International Interconnect Technology Conference, IITC 2009

Volumn , Issue , 2009, Pages 63-65

  Shapiro, M ^a   Interrante, M ^a   Andry, P ^b   Dang, B ^b   Tsang, C ^b   Liptak, R ^a   Griffith, J ^a   Sprogis, E ^a   Guerin, L ^c   Truong, V ^c   Berger, D ^a   Knickerbocker, J ^b  

^a IBM MICROELECTRONICS   (United States)

^b IBM RESEARCH   (United States)

^c IBM CANADA LTD   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

3D-CHIP STACKING TECHNOLOGY; CMOS PROCESSING; HIGH TEMPERATURE; KEY FEATURE; LEAKAGE PATHS; THERMAL OXIDES; THROUGH SILICON VIAS;

INTERCONNECTION NETWORKS; SILICON WAFERS; THREE DIMENSIONAL; TUNGSTEN;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 70349437463     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.2009.5090341     Document Type: Conference Paper

References (3)

1. J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, M. J. Interrante, C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E. J. Sprogis, S. M. Sri-Jayantha, A. M. Stephens, A. W. Topol, C. K. Tsang, B. C. Webb, and S. L. Wright, "Three-dimensional silicon integration," IBM J. Res. & Dev., vol. 52, no. 6, pp. 553-569, 2008.
2. B. Dang, S. L. Wright, P. S. Andry, E. J. Sprogis, C. K. Tsang, M. J. Interrante, B. C. Webb, R. J. Polastre, R. R. Horton, C. S. Patel, A. Sharma, J. Zheng, K. Sakuma, J. U. Knickerbocker, "3D chip stacking with C4 technology," IBM J. Res. & Dev., vol. 52, no. 6, pp. 599-609, 2008.
3. M. Kawano, S. Uchiyama, Y. Egawa, N. Takahashi, Y. Kurita, K. Soejima, M. Komuro, et al., "A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer," Proceedings of the IEDM International Electron Devices Meeting, San Francisco, CA, 2006, pp. 1-4.