A quantization error minimization method using DDS-DAC for wideband fractional-N frequency synthesizer

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 11, 2010, Pages 2283-2291

  Wu, Yi Da ^a   Lai, Chang Ming ^a   Lee, Chao Cheng ^b   Huang, Po Chiun ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

^b REALTEK SEMICONDUCTOR CORP   (Taiwan)

Author keywords

DAC; direct digital synthesis; fractional N synthesizer; low phase noise

Indexed keywords

1.8 GHZ; CLOSED-LOOP BANDWIDTH; COMPENSATION MECHANISM; DAC; DIRECT DIGITAL SYNTHESIS; FRACTIONAL DIVIDER; FRACTIONAL DIVISION; FRACTIONAL-N FREQUENCY SYNTHESIZERS; FRACTIONAL-N SYNTHESIZER; IN-BAND NOISE; LOOP BANDWIDTH; LOW PHASE NOISE; MULTI-MODULUS; NOISE REDUCTIONS; PROTOTYPE CHIP; PULSE CONVERTER; QUANTIZATION ERRORS; SETTLING TIME; SIGMA-DELTA; WIDE-BAND;

BANDWIDTH; DIRECT DIGITAL CONTROL SYSTEMS; ERROR COMPENSATION; FREQUENCY SYNTHESIZERS; PHASE NOISE;

DIGITAL INTEGRATED CIRCUITS;

EID: 77958598997     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2064013     Document Type: Conference Paper

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