Panoptic DVS: A fine-grained dynamic voltage scaling framework for energy scalable CMOS Design

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2009, Pages 491-497

  Putic, Mateja ^a   Di, Liang ^b   Calhoun, Benton H ^a   Lach, John ^a  

^a UNIVERSITY OF VIRGINIA   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHM-LEVEL; APPLICATION PERFORMANCE; BATTERY LIFETIME; CIRCUIT STRUCTURES; CMOS DESIGN; CO-DESIGN METHODOLOGY; DYNAMIC VOLTAGE SCALING; ENERGY SAVING; MULTIPLE COMPONENTS; PROCESSING RATES; RATE CONTROLS; SCALABLE ARCHITECTURES; SUB-BLOCKS; TEST CHIPS;

CMOS INTEGRATED CIRCUITS; ENERGY CONSERVATION; ENERGY EFFICIENCY; VOLTAGE STABILIZING CIRCUITS;

DESIGN;

EID: 77951002245     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2009.5413110     Document Type: Conference Paper

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