Strain engineering in nanoscale CMOS FinFETs and methods to optimize R S/D

Proceedings of 2010 International Symposium on VLSI Technology, System and Application, VLSI-TSA 2010

Volumn , Issue , 2010, Pages 156-157

  Smith, Casey ^a   Parthasarathy, Srivatsan ^b   Coss, Brian E ^c   Williams, Jason ^d   Adhikari, Hemant ^e   Smith, Greg ^a   Sassman, Barry ^a   Hussain, Muhammad Mustafa ^a   Majhi, Prashant ^f   Jammy, Raj ^a  

^a SEMATECH   (United States)

^b UNIVERSITY OF FLORIDA   (United States)

^c UNIVERSITY OF TEXAS AT DALLAS   (United States)

^d TEXAS STATE UNIVERSITY   (United States)

^e AMD ^*  (United States)

^f INTEL CORPORATION   (United States)

Author keywords

Biaxial stress; CESL; FinFET; RS D; Stressor

Indexed keywords

BIAXIAL STRESS; CESL; FINFET; RS/D; STRESSOR;

NANOTECHNOLOGY;

INTEGRATED CIRCUITS;

EID: 77957921467     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2010.5488905     Document Type: Conference Paper

References (9)

1. M. Guillorn, et. al., VLSI Tech. Symp., pp12-13 (2008);
2. A. Yagashita et. al., JJAP 43(4B), pp. 1713-1716 (2004);
3. S. Suthram et. al., EDL 28(1), (2007);
4. V. Trivedi et. al., Trans. Elec. Dev. 52(1), pp. 56-62 (2005);
5. M.C. Ozturk, J. Liu, AIP Conf. Proc., p6 (2005);
6. C. Ohler et. al., Phys. Rev. B 58, pp7864-7871 (1998);
7. G. Ghibaudo, Electronics Letters: 24 (9), pp. 543-545 (1988);
8. C.-H. Hsu et. al, VLSI-TSA, pp1-2 (2007);
9. S. Suthram et. al., VLSI-TSA, pp163-164 (2008)