Scale-length assessment of the trigate bulk MOSFET design

IEEE Transactions on Electron Devices

Volumn 56, Issue 11, 2009, Pages 2840-2842

  Sun, Xin ^a   Liu, Tsu Jae King ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

MOSFET; Multigate FET; Scale length

Indexed keywords

BULK MOSFET; DEVICE DESIGN; DOUBLE-GATE SOI MOSFET; MOSFET; MOSFETS; MULTIGATE FET; SCALABLE DESIGN; SCALE LENGTH; TRIGATE;

FIELD EFFECT TRANSISTORS; LOGIC DESIGN; MESFET DEVICES; SOLID-STATE SENSORS;

MOSFET DEVICES;

EID: 70350724399     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2009.2030711     Document Type: Article

References (6)

1. R.-H. Yan, A. Ourmazd, and K. F. Lee, "Scaling the Si MOSFET: From bulk to SOI to bulk," IEEE Trans. Electron Devices, vol. 39, no. 7, pp. 1704-1710, Jul. 1992.
2. K. Suzuki, T. Tanaka, Y. Tosaka, H. Horie, and Y. Arimoto, "Scaling theory for double-gate SOI MOSFETs," IEEE Trans. Electron Devices vol. 40, no. 12, pp. 2326-2329, Dec. 1993.
3. D. J. Frank, Y. Taur, and H.-S. P. Wong, "Generalized scale length for two-dimensional effects in MOSFETs," IEEE Electron Device Lett., vol. 19, no. 10, pp. 385-387, Oct. 1998.
4. X. Sun, Q. Lu, V. Moroz, H. Takeuchi, G. Gebara, J. Wetzel, S. Ikeda, C. Shin, and T.-J. K. Liu, "Tri-gate bulk MOSFET design for CMOS scaling to the end of the roadmap," IEEE Electron Device Lett., vol. 29, no. 5, pp. 491-493, May 2008.
5. K. Akarvardar, A. Mercha, S. Cristoloveanu, P. Gentil, E. Simoen, V. Subramanian, and C. Claeys, "A two-dimensional model for interface coupling in triple-gate transistors," IEEE Trans. Electron Devices vol. 54, no. 4, pp. 767-775, Apr. 2007.
6. K. K. Young, "Short-channel effect in fully-depleted SOI MOSFETs," IEEE Trans. Electron Devices, vol. 36, no. 2, pp. 399-402, Feb. 1989.