Power-aware multi-objective evolutionary optimisation for application mapping on network-on-chip platforms

International Journal of Electronics

Volumn 97, Issue 10, 2010, Pages 1163-1179

  Da Silva, M V C ^a   Nedjah, N ^a   Mourelle, L M ^a  

^a STATE UNIVERSITY OF RIO DE JANEIRO   (Brazil)

Author keywords

application mapping; evolutionary computation; multi objective optimisation; network on chip

Indexed keywords

APPLICATION MAPPING; COMBINATORIAL PROBLEM; COMMUNICATION INFRASTRUCTURE; DECISION MAKERS; EVOLUTIONARY COMPUTATIONS; EVOLUTIONARY OPTIMISATION; EXECUTION TIME; INTELLECTUAL PROPERTY BLOCKS; MICRO-GA; MULTI OBJECTIVE; MULTI OBJECTIVE EVOLUTIONARY ALGORITHMS; MULTIOBJECTIVE OPTIMISATION; NETWORK ON CHIP; NOC DESIGN; NSGA-II; OPTIMISATIONS; PHYSICAL MAPPING; PLATFORM-BASED DESIGN METHODOLOGY; POWER CONSUMPTION; POWER-AWARE;

MAPPING; MULTIOBJECTIVE OPTIMIZATION; ROUTERS; SERVERS; VLSI CIRCUITS;

EVOLUTIONARY ALGORITHMS;

EID: 77957895654     PISSN: 00207217     EISSN: 13623060     Source Type: Journal    
DOI: 10.1080/00207217.2010.512105     Document Type: Article

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