Reliability studies on a 45nm low power system-on-chip (SOC) dual gate oxide high-K / metal gate (DG HK+MG) technology

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2010, Pages 293-298

  Prasad, C ^a   Bai, P ^a   Gannavaram, S ^a   Hafez, W ^a   Hicks, J ^a   Jan, C H ^a   Lin, J ^a   Jones, M ^a   Komeyli, K ^a   Kotlyar, R ^a   Mistry, K ^a   Post, I ^a   Tsai, C ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DUAL GATE OXIDE; DUAL GATES; LOW-POWER SYSTEMS; METAL GATE; MG TECHNOLOGIES; PROCESS OPTIMIZATION; RELIABILITY CHARACTERIZATION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; PROGRAMMABLE LOGIC CONTROLLERS;

RELIABILITY;

EID: 77957889796     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2010.5488815     Document Type: Conference Paper

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