메뉴 건너뛰기




Volumn , Issue , 2010, Pages 104-109

Efficient high level synthesis exploration methodology combining exhaustive and gradient-based pruned searching

Author keywords

[No Author keywords available]

Indexed keywords

DATA PATHS; DESIGN SPACES; EFFICIENT DESIGNS; EXPLORATION METHODS; GLOBALOPTIMUM; GRADIENT BASED; HIGH LEVEL SYNTHESIS; LEVEL TRANSFORMATION; PRUNING TECHNIQUES; QUALITY DESIGN; QUALITY OF DESIGN; RUNTIMES; SECOND LEVEL; SOLUTION SPACE;

EID: 77957889333     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2010.56     Document Type: Conference Paper
Times cited : (20)

References (21)
  • 2
    • 9644281035 scopus 로고    scopus 로고
    • Methods for evaluating and covering the design. space during early design. development
    • M. Gries, "Methods for Evaluating and Covering the Design. Space during Early Design. Development," Integr. VLSI J., vol. 38, no. 2, pp. 131-183, 2004.
    • (2004) Integr. VLSI J. , vol.38 , Issue.2 , pp. 131-183
    • Gries, M.1
  • 9
    • 0031098179 scopus 로고    scopus 로고
    • A solution methodology for exact design space exploration in a three-dimensional design space
    • S. Chaudhuri, S. A. Blythe, and R. A. Walker, "A Solution Methodology for Exact Design Space Exploration in a Three-Dimensional Design Space," IEEE Trans. Very Large Scale Integr. Syst., vol. 5, no. 1, pp. 69-81, 1997.
    • (1997) IEEE Trans. Very Large Scale Integr. Syst. , vol.5 , Issue.1 , pp. 69-81
    • Chaudhuri, S.1    Blythe, S.A.2    Walker, R.A.3
  • 10
    • 35148892375 scopus 로고    scopus 로고
    • Exploring time/resource trade-offs by solving dual scheduling problems with the ant colony optimization
    • G. Wang, W. Gong, B. DeRenzi, and R. Kastner, "Exploring Time/Resource Trade-offs by Solving Dual Scheduling Problems with the Ant Colony Optimization," ACM Trans. Design Autom. Electr. Syst., vol. 12, no. 4, 2007.
    • (2007) ACM Trans. Design Autom. Electr. Syst. , vol.12 , Issue.4
    • Wang, G.1    Gong, W.2    DeRenzi, B.3    Kastner, R.4
  • 12
    • 52049101394 scopus 로고    scopus 로고
    • Optimal unroll. factor for reconfigurable architectures
    • O. Dragomir, E. Panainte, K. Bertels, and S. Wong, "Optimal Unroll. Factor for Reconfigurable Architectures," in Proc. of ARC, 2008, pp. 4-14.
    • (2008) Proc. of ARC , pp. 4-14
    • Dragomir, O.1    Panainte, E.2    Bertels, K.3    Wong, S.4
  • 13
    • 0033680150 scopus 로고    scopus 로고
    • A methodology and tool for automated transformational high-level. design space exploration
    • J. Gerlach and W. Rosenstiel, "A Methodology and Tool for Automated Transformational High-Level. Design Space Exploration," in ICCD, 2000, pp. 545-548.
    • (2000) ICCD , pp. 545-548
    • Gerlach, J.1    Rosenstiel, W.2
  • 14
    • 0030651922 scopus 로고    scopus 로고
    • Built-in chaining: Introducing complex components into architectural synthesis
    • P. Marwedel, B. Landwehr, R. Domer, "Built-in Chaining: Introducing Complex Components into Architectural Synthesis," in Proc. of the ASPDAC, 1997, pp. 599-605.
    • (1997) Proc. of the ASPDAC , pp. 599-605
    • Marwedel, P.1    Landwehr, B.2    Domer, R.3
  • 17
    • 77957898849 scopus 로고    scopus 로고
    • The ExPRESS group
    • The ExPRESS group, "http://express.ece.ucsb.edu," 2009.
    • (2009)
  • 18
    • 30744468841 scopus 로고    scopus 로고
    • Coordinated parallelizing compiler optimizations and high-level synthesis
    • S. Gupta, N. Dutt, R. Gupta, and A. Nicolau, "Coordinated Parallelizing Compiler Optimizations and High-Level Synthesis," ACM Trans. Des. Autom. Electron. Syst, vol. 9, p. 2004, 2002.
    • (2002) ACM Trans. Des. Autom. Electron. Syst , vol.9 , pp. 2004
    • Gupta, S.1    Dutt, N.2    Gupta, R.3    Nicolau, A.4
  • 20
    • 77957920594 scopus 로고    scopus 로고
    • Synopsys Inc.
    • Synopsys Inc., "www.synopsys.com/products/," 2009.
    • (2009)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.