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Volumn , Issue , 2007, Pages 391-396

The impact of loop unrolling on controller delay in high level synthesis

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; HIGH LEVEL LANGUAGES; OPTIMAL CONTROL SYSTEMS; OPTIMIZATION; TIME DELAY;

EID: 34548354777     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364623     Document Type: Conference Paper
Times cited : (29)

References (18)
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    • Hosangadi, A.1
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    • M. Potkonjak and J. Rabaey, "Optimizing resource utilization using transformations," IEEE TCAD, 13(3), 1994.
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    • Using speculative computation and parallelizing techniques to improve scheduling of control based designs
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  • 10
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    • Gupta, S.1
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    • S. Park and K. Choi, "Performance-driven high-level synthesis with bit-level chaining and clock selection," IEEE TCAD, 20(2), 2001.
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    • Park, S.1    Choi, K.2
  • 12
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    • Bitwise scheduling to balance the computational cost of behavioral specifications
    • M. C. Molina, et al, "Bitwise scheduling to balance the computational cost of behavioral specifications," IEEE TCAD, 25(1), 2006.
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  • 15
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.