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1
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8744241430
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The MOLEN Polymorphic Processor
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October
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Vassiliadis, S., Wong, S., Gaydadjiev, G.N., Bertels, K., Kuzmanov, G., Panainte, E.M.: The MOLEN Polymorphic Processor. IEEE Transactions on Computers, 1363-1375, (October 2004)
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(2004)
IEEE Transactions on Computers
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Vassiliadis, S.1
Wong, S.2
Gaydadjiev, G.N.3
Bertels, K.4
Kuzmanov, G.5
Panainte, E.M.6
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2
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Panainte, E.M., Bertels, K., Vassiliadis, S.: The PowerPC Backend Molen Compiler. In: Becker, J., Platzner, M., Vernalde, S. (eds.) FPL 2004. LNCS, 3203, pp. 434-443. Springer, Heidelberg (2004)
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Panainte, E.M., Bertels, K., Vassiliadis, S.: The PowerPC Backend Molen Compiler. In: Becker, J., Platzner, M., Vernalde, S. (eds.) FPL 2004. LNCS, vol. 3203, pp. 434-443. Springer, Heidelberg (2004)
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3
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48149091918
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DWARV: DelftWorkbench Automated Reconfigurable VHDL Generator
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August, 2007
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Yankova, Y.D., Kuzmanov, G., Bertels, K., Gaydadjiev, G., Lu, J., Vassiliadis, S.: DWARV: DelftWorkbench Automated Reconfigurable VHDL Generator. In: The 17th International Conference on Field Programmable Logic and Applications (FPL 2007) (August 2007), pp. 697-701 (2007)
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(2007)
The 17th International Conference on Field Programmable Logic and Applications (FPL
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Yankova, Y.D.1
Kuzmanov, G.2
Bertels, K.3
Gaydadjiev, G.4
Lu, J.5
Vassiliadis, S.6
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4
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Guo, Z., Buyukkurt, B., Najjar, W., Vissers, K.: Optimized Generation of datapath from C codes for FPGAs. In: DATE 2005: Proceedings of the conference on Design, Automation and Test in Europe (March 2005), pp. 112-117 (2005)
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Guo, Z., Buyukkurt, B., Najjar, W., Vissers, K.: Optimized Generation of datapath from C codes for FPGAs. In: DATE 2005: Proceedings of the conference on Design, Automation and Test in Europe (March 2005), pp. 112-117 (2005)
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Gupta, S., Dutt, N., Gupta, R., Nicolau, A.: Loop shifting and compaction for the high-level synthesis of designs with complex control flow. In: DATE 2004: Proceedings of the conference on Design, Automation and Test in Europe (February 2004), pp. 114-119 (2004)
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Gupta, S., Dutt, N., Gupta, R., Nicolau, A.: Loop shifting and compaction for the high-level synthesis of designs with complex control flow. In: DATE 2004: Proceedings of the conference on Design, Automation and Test in Europe (February 2004), pp. 114-119 (2004)
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Mei, B., Vernalde, S., Verkest, D., Man, H.D., Lauwereins, R.: Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling. In: DATE 2003: Proceedings of the conference on Design, Automation and Test in Europe (March 2003), pp. 296-301 (2003)
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Mei, B., Vernalde, S., Verkest, D., Man, H.D., Lauwereins, R.: Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling. In: DATE 2003: Proceedings of the conference on Design, Automation and Test in Europe (March 2003), pp. 296-301 (2003)
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7
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35048884179
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Modeling loop unrolling: Approaches and open issues
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Pimentel, A.D, Vassiliadis, S, eds, SAMOS, Springer, Heidelberg
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Cardoso, J.M.P., Diniz, P.C.: Modeling loop unrolling: approaches and open issues. In: Pimentel, A.D., Vassiliadis, S. (eds.) SAMOS 2004. LNCS, vol. 3133, pp. 224-233. Springer, Heidelberg (2004)
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LNCS
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Cardoso, J.M.P.1
Diniz, P.C.2
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Liao, J., Wong, W.F., Mitra, T.: A model for hardware realization of kernel loops. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, 2778, pp. 334-344. Springer, Heidelberg (2003)
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Liao, J., Wong, W.F., Mitra, T.: A model for hardware realization of kernel loops. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 334-344. Springer, Heidelberg (2003)
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Banerjee, S., Bozorgzadeh, E., Dutt, N.: PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures. In: ASP-DAC 2006: Proceedings of the 2006 conference on Asia South Pacific design automation (January 2006), pp. 491-496 (2006)
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Banerjee, S., Bozorgzadeh, E., Dutt, N.: PARLGRAN: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures. In: ASP-DAC 2006: Proceedings of the 2006 conference on Asia South Pacific design automation (January 2006), pp. 491-496 (2006)
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