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Volumn , Issue , 2010, Pages 3-12

Automated synthesis of instruction codes in the context of micro-architecture design

Author keywords

Asynchronous control; Instruction set; Microarchitecture; Partial orders; Synthesis

Indexed keywords

ASYNCHRONOUS CONTROL; INSTRUCTION SET; MICRO ARCHITECTURES; PARTIAL ORDER; SYNTHESIS;

EID: 77957594425     PISSN: 15504808     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSD.2010.30     Document Type: Conference Paper
Times cited : (1)

References (14)
  • 6
    • 77957551767 scopus 로고    scopus 로고
    • Processor Modelling and Design Tools
    • Chapter 8, by L. Sheffer, L. Lavagno, and G. Martin, Taylor and Francis Group.
    • P. Mishra and N. Dutt. Processor Modelling and Design Tools, Chapter 8 in 'EDA for IC Systems Design, Verification, and Testing' by L. Sheffer, L. Lavagno, and G. Martin. Taylor and Francis Group, 2006.
    • (2006) EDA for IC Systems Design, Verification, and Testing
    • Mishra, P.1    Dutt, N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.