Instruction encoding synthesis for architecture exploration using hierarchical processor models

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 262-267

  Nohl, Achim ^a   Greive, Volker ^a   Braun, Gunnar ^a   Hoffmann, Andreas ^a   Leupers, Rainer ^b   Schliebusch, Oliver ^b   Meyr, Heinrich ^b  

^a CoWare Inc ^*  (United States)

^b RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

Instruction Encoding; Instruction Set Architectures

Indexed keywords

COMPUTER ARCHITECTURE; HIERARCHICAL SYSTEMS; PROBLEM SOLVING; PROGRAM PROCESSORS;

ARCHITECTURE EXPLORATION;

ENCODING (SYMBOLS);

EID: 0042134898     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/775894.775898     Document Type: Conference Paper

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