Spur-reduction techniques for PLLs using sub-sampling phase detection

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 474-475

  Gao, Xiang ^a   Klumperink, Eric A M ^a   Socci, Gerard ^b   Bohsali, Mounir ^b   Nauta, Bram ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

^b NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL LINES; DESIGN TECHNIQUE; FREQUENCY RATIOS; LOOP BANDWIDTH; LOOP FILTER; ON CHIPS; PHASE DETECTION; REDUCTION TECHNIQUES; REFERENCE SPUR; SETTLING TIME; SUB-SAMPLING;

BANDWIDTH; FREQUENCY MULTIPLYING CIRCUITS; VARIABLE FREQUENCY OSCILLATORS;

PHASE LOCKED LOOPS;

EID: 77952194120     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433841     Document Type: Conference Paper

References (5)

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